A person skilled in the art will appreciate that the concepts disclosed herein are applicable to digital integrated circuits (IC), examples of which include, but are not limited to Low Voltage Complementary Metal Oxide Semiconductors (LVCMOS), Low Voltage Transistor-Transistor Logic (LVTTL), High-Speed Transceiver Logic (HSTL), Stub Series Terminated Logic (SSTL), and the like.
One of the challenges in design of output circuitry of digital ICs is satisfying current and voltage requirements dictated by a load connected to the output circuitry, while at the same time achieving a high maximum frequency (Fmax) and low delay of the signal processed by the digital IC. In general, a signal processed by digital ICs comprises a pulse train of a generally variable duty cycle. An ideal pulse train alternates instantaneously between two levels—a low level and a high level, represented by, for example, voltage or current. The up and down transitions between the low level high levels are called the rising edge and the falling edge. The duty cycle, i.e., length of time spent at the low levels and time spent at the high level varies and is determined by the information carried by the signal.
In practice, the instantaneous alternation is never achieved because of physical limitations of the system that generates the waveform. The times taken for the signal to rise from a low level to a high level and back again are called the “rise time” and the “fall time” respectively. The term “rise time” refers to the time required for the signal to change from a specified value of the low level to a specified value of the high level, and the term “fall time” refers to the time required for the signal to change from the specified value of the high level to the specified value of the low level. In other words, the rise time is the time required for the response to rise from x % to y % of its final value. Often the specified values are 10% and 90% of the difference between the high level and the low level.
A conceptual output circuitry 100 as known in the art is illustrated in FIG. 1. A signal to be processed by the output circuitry 100 originates inside of the IC and is conceptually depicted as a signal source 102. In general signal to be processed comprises data. The signal is provided to an input of a pre-driver 104. The task of the pre-driver 104 is to properly condition the signal, i.e., to provide a signal with a proper shape to an output driver 106. The task of the, output driver 106 is to amplify the signal to satisfying current and voltage requirements dictated by a load 108.
FIG. 2 illustrates further details of possible implementation of conceptual block diagram of FIG. 1. By means of example, the topology of the driver 106 of FIG. 1 may comprise a pair of P-Channel MOS transistor 206a and an N-channel MOS transistor 206b as depicted in FIG. 2 When such an output stage is driven by a signal form the pre-driver 204, there is a certain period of time, when both the P-channel MOS transistor 206a, and the N-channel MOS transistor 206b would be simultaneously “ON”, i.e., the transistors are simultaneously conducting a current for a certain period of time. Such a current is known as crowbar current (Icrowbar) flowing through both of the transistors. The crowbar current causes voltage change at the power supply VDDS and VSS and power ground nodes (not shown); which in turn causes degradation of the signal.
Because of the finite frequency response of the P-channel MOS transistor 206a and the N-channel MOS transistor 206b decreasing the rise time respectively the fall time of the single signal would not prevent both the P-channel MOS transistor 206a, and the N-channel MOS transistor 206b to be ON for a certain period of time. Furthermore, decreasing the rise time respectively the fall time causes a derivative of current with time (di/dt) to increase. Such increase of di/dt further contributes to voltage change at the power supply and power ground nodes.
An improvement on the single signal solution known in the art modified the pre-driver 104 to comprise a not-AND (NAND) circuit 204a configured so that the falling edge of the NAND voltage signal turns on the P-channel MOS transistor 206a and a not-OR (NOR) circuit 204b configured so that the falling edge of the NOR voltage signal turns on the N-channel MOS transistor 206b. The inclusion of the NAND 204a and NOR 204b circuitry caused the shaping of the signal driving the P-channel MOS transistor 206a and the N-channel MOS transistor 206b to turn on at slightly different times; consequently decreasing the time when both the P-channel MOS transistor 206a, and the N-channel MOS transistor 206b are ON; thus decreasing the di/dt as well as the crowbar current. Such improvement is due to asymmetry between the turn on and turn off times of the NAND 204a and NOR 204b circuits—the falling edge of the output voltage of the NAND circuit 204a is slower than the falling edge of the output voltage of the NOR circuit 204b, while the rising edge of the output voltage of the NAND circuit 204a is faster than the rising edge of the output voltage of the NOR circuit 204b. 
As illustrated in FIG. 2, although not always implemented, the pre-driver circuit comprising the NAND 204a and NOR 204b circuitry is provided with the signal to be processed 202 as well as a control signal 201, which enables and disables the at the pre-driver circuit 204 processing of the signal by the output circuitry 200.
However, there is a need in the art for a further improvement in the decrease of the di/dt as well as the crowbar current.